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ISL12023
Real Time Clock with On Chip Temp Compensation 5ppm
Data Sheet June 24, 2009 FN6682.2
Low Power RTC with Battery-Backed SRAM and Embedded Temp Compensation 5ppm with Auto Daylight Saving
The ISL12023 device is a low power real time clock with an embedded Temp sensor for oscillator compensation, clock/calendar, power fail, low battery monitor, brownout indicator, single periodic or polled alarms, intelligent battery-backup switching, Battery ResealTM function and 128 bytes of battery-backed user SRAM. The oscillator uses an external, low-cost 32.768kHz crystal. The real time clock tracks time with separate registers for hours, minutes, and seconds. The device has calendar registers for date, month, year and day of the week. The calendar is accurate through 2099, with automatic leap year correction. Daylight Savings time adjustment is done automatically, using parameters entered by the user. Power fail and battery monitors offer user-selectable trip levels. A time stamp function records the time and date of switchover from VDD to VBAT power, and also from VBAT to VDD power.
Features
* Real Time Clock/Calendar - Tracks Time in Hours, Minutes and Seconds - Day of the Week, Day, Month and Year * On-chip Oscillator Compensation Over the Operating Temp Range - 5ppm Over -40C to +85C * 10-bit Digital Temperature Sensor Output - 2C Accuracy * Customer Programmable Day Light Saving Time * Clock Output with 15 Selectable Frequencies * 1 Alarm - Settable to the Second, Minute, Hour, Day of the Week, Day, or Month - Single Event or Pulse Interrupt Mode * Battery ResealTM Function to Extend Battery Shelf Life * Automatic Backup to Battery or Super Capacitor - Operation to VBAT = 1.8V - 1.0A Battery Supply Current * Battery Status Monitor - 2 User Programmable Levels - Seven Selectable Voltages for Each Level
Pinout
ISL12023 (14 LD TSSOP) TOP VIEW
NC X1 X2 VBAT GND LVRST NC 1 2 3 4 5 6 7 14 13 12 11 10 9 8 NC VDD IRQ SCL SDA FOUT NC
* Power Status Brownout Monitor - Six Selectable Trip Levels, from 2.295V to 4.675V * Oscillator Failure Detection * Time Stamp for First VDD to VBAT, and Last VBAT to VDD * 128 Bytes Battery-Backed User SRAM * Separate FOUT, IRQ, and LVRST Outputs * I2C BusTM - 400kHz Clock Frequency * 14 Ld TSSOP Package * Pb-Free (RoHS Compliant)
Applications
* Utility Meters * POS Equipment * Medical Devices * Security Systems * Vending Machines * White Goods * Printers and Copiers 1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. I2C BusTM is a trademark owned by NXP Semiconductors Netherlands, B.V. Copyright Intersil Americas Inc. 2008, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL12023 Ordering Information
PART NUMBER (Note) ISL12023IVZ* PART MARKING 12023 IVZ VDD RANGE (V) 2.7 to 5.5 TEMP RANGE (C) -40 to +85 PACKAGE (Pb-Free) 14 Ld TSSOP PKG. DWG. # M14.173
*Add "-T" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020
Block Diagram
SDA SCL SDA BUFFER SCL BUFFER I2C INTERFACE SECONDS CONTROL LOGIC REGISTERS MINUTES HOURS DAY OF WEEK CRYSTAL OSCILLATOR RTC DIVIDER DATE MONTH VDD VTRIP SWITCH VBAT GND TEMPERATURE SENSOR FREQUENCY CONTROL BROWNOUT ALARM FOUT LVRST INTERNAL SUPPLY IRQ POR FREQUENCY OUT YEAR
ALARM
X1 X2
CONTROL REGISTERS USER SRAM
Pin Descriptions
PIN NUMBER 1, 7, 8, 14 2 3 4 5 6 9 10 11 12 13 SYMBOL NC X1 X2 VBAT GND LVRST FOUT SDA SCL IRQ VDD No connect. Do not connect. Crystal Input. The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal. X1 can also be driven directly from a 32.768kHz source. Crystal Output. The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal. X2 should be left open when X1 is driven from external source. Backup Supply. This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event that the VDD supply fails. This pin should be tied to ground if not used. Ground. Low Voltage Reset pin for VCC Brownout Mode. Open drain configuration Frequency Output. Frequency selectable through Control Register. Open drain configuration. Serial Data. SDA is a bi-directional pin used to transfer serial data into and out of the device. It has an open drain output and may be wire OR'ed with other open drain or open collector outputs. Serial Clock. The SCL input is used to clock all serial data into and out of the device. Interrupt Output. Provides active low interrupt signal. Open drain configuration. Power Supply. DESCRIPTION
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ISL12023
Absolute Maximum Ratings
Voltage on VDD, VBAT and IRQ/FOUT pins (respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Voltage on SCL and SDA pins (respect to ground) . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V Voltage on X1 and X2 pins (respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.5V ESD Rating Human Body Model (Per MIL-STD-883 Method 3014) . . . . .>3kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>300V
Thermal Information
Thermal Resistance (Typical, Note 1) JA (C/W) 14 Ld TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTE: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
DC Operating Characteristics-RTC Test Conditions: VDD = +2.7V to +5.5V, TA = -40C to +85C, unless otherwise stated.
SYMBOL VDD VBAT IDD1 PARAMETER Main Power Supply Battery Supply Voltage Supply Current. (I2C not Active, Temperature Conversion not Active, FOUT not Active) IDD2 IDD3 CONDITIONS (Note 11) (Note 11) VDD = 5V VDD = 3V MIN (Note 9) 2.7 1.8 4.1 3.5 200 120 TYP (Note 5) MAX (Note 9) 5.5 5.5 7 6 500 400 UNITS V V A A A A 2 3, 4 3, 4 3, 4 3, 4 NOTES
Supply Current. (I2C Active, Temperature VDD = 5V Conversion not Active, FOUT not Active) Supply Current. (I2C not Active, Temperature Conversion Active, FOUT not Active) Battery Supply Current VDD = 5V
IBAT
VDD = 0V, VBAT = 3V, TA = +25C VBAT = 3V
1.0 1.0
1.6 5.0 100
A A nA A A mV mV V mV mV
3 3
IBATLKG ILI ILO VBATM VPBM VTRIP VTRIPHYS VBATHYS FoutT FoutV ATLSB Temp
Battery Input Leakage Input Leakage Current on SCL I/O Leakage Current on SDA Battery Level Monitor Threshold Brownout Level Monitor Threshold VBAT Mode Threshold VTRIP Hysteresis VBAT Hysteresis Frequency Stability vs Temperature Frequency Stability vs Voltage AT Sensitivity per LSB Temperature Sensor Accuracy
VDD = 5.5V, VBAT = 1.8V -1.0 -1.0 -100 -100 (Note 11) 2.0 2.2 30 50 2.7V VDD 3.6V, 2.7V VDD 3.6V BETA (3:0) = 1000 VDD = VBAT = 3.3 V -5 -3 0.5 1 2 0.1 0.1
1.0 1.0 +100 +100 2.4
7 7 10 10 10 7
+5 +3 2
ppm ppm ppm C
IRQ, LVRST, FOUT VOL Output Low Voltage VDD = 5V, IOL = 3mA VDD = 2.7V, IOL = 1mA 0.4 0.4 V V
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Power-Down Timing
SYMBOL VDD SRTest Conditions: VDD = +2.7 to +5.5V, TA = -40C to +85C, unless otherwise stated. PARAMETER VDD Negative Slew Rate CONDITIONS MIN (Note 9) TYP (Note 5) MAX (Note 9) 10 UNITS V/ms NOTES 6
I2C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, TA = -40C to +85C, unless otherwise specified.
SYMBOL VIL VIH Hysteresis VOL CPIN PARAMETER SDA and SCL Input Buffer LOW Voltage SDA and SCL Input Buffer HIGH Voltage SDA and SCL Input Buffer Hysteresis SDA Output Buffer LOW Voltage, Sinking 3mA SDA and SCL Pin Capacitance VDD = 5V, IOL = 3mA TA = +25C, f = 1MHz, VDD = 5V, VIN = 0V, VOUT = 0V TEST CONDITIONS MIN (Note 9) -0.3 0.7 x VDD 0.05 x VDD 0 0.02 0.4 10 TYP (Note 5) MAX (Note 9) 0.3 x VDD VDD + 0.3 UNITS V V V V pF 7, 8 7, 8 NOTES
fSCL tIN tAA
SCL Frequency Pulse Width Suppression Time at SDA and SCL Inputs SCL Falling Edge To SDA Output Data Valid Time the Bus must be Free Before the Start of a New Transmission Any pulse narrower than the max spec is suppressed. SCL falling edge crossing 30% of VDD, until SDA exits the 30% to 70% of VDD window. SDA crossing 70% of VDD during a STOP condition, to SDA crossing 70% of VDD during the following START condition. Measured at the 30% of VDD crossing. Measured at the 70% of VDD crossing. SCL rising edge to SDA falling edge. Both crossing 70% of VDD. From SDA falling edge crossing 30% of VDD to SCL falling edge crossing 70% of VDD. From SDA exiting the 30% to 70% of VDD window, to SCL rising edge crossing 30% of VDD. From SCL falling edge crossing 30% of VDD to SDA entering the 30% to 70% of VDD window. From SCL rising edge crossing 70% of VDD, to SDA rising edge crossing 30% of VDD. 1300
400 50 900
kHz ns ns
tBUF
ns
tLOW tHIGH tSU:STA
Clock LOW Time Clock HIGH Time START Condition Setup Time
1300 600 600
ns ns ns
tHD:STA
START Condition Hold Time
600
ns
tSU:DAT
Input Data Setup Time
100
ns
tHD:DAT
Input Data Hold Time
0
900
ns
tSU:STO
STOP Condition Setup Time
600
ns
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ISL12023
I2C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, TA = -40C to +85C, unless otherwise specified. (Continued)
SYMBOL tHD:STO PARAMETER STOP Condition Hold Time TEST CONDITIONS From SDA rising edge to SCL falling edge. Both crossing 70% of VDD. From SCL falling edge crossing 30% of VDD, until SDA enters the 30% to 70% of VDD window. From 30% to 70% of VDD. From 70% to 30% of VDD. Total on-chip and off-chip Maximum is determined by tR and tF. For Cb = 400pF, max is about 2k~2.5k. For Cb = 40pF, max is about 15k~20k MIN (Note 9) 600 TYP (Note 5) MAX (Note 9) UNITS ns NOTES
tDH
Output Data Hold Time
0
ns
tR tF Cb RPU
SDA and SCL Rise Time SDA and SCL Fall Time Capacitive Loading of SDA or SCL SDA and SCL Bus Pull-up Resistor Off-chip
20 + 0.1 x Cb 20 + 0.1 x Cb 10 1
300 300 400
ns ns pF k
8 8 8 8
NOTES: 2. Temperature Conversion is inactive below VBAT = 2.7V. Device operation is not guaranteed at VBAT<1.8V. 3. IRQ/FOUT Inactive. 4. VDD > VBAT +VBATHYS 5. Specified at +25C. 6. In order to ensure proper timekeeping, the VDD SR- specification must be followed. 7. Limits should be considered typical and are not production tested. 8. These are I2C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specification. 9. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 10. Specifications are typical and require using a recommended crystal (see "Application Section" on page 24). 11. Minimum VDD and/or VBAT of 1V to sustain the SRAM. The value is based on characterization and it is not tested.
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FN6682.2 June 24, 2009
ISL12023 SDA vs SCL Timing
tF tHIGH tLOW tR
SCL tSU:STA tHD:STA SDA (INPUT TIMING)
tSU:DAT tHD:DAT tSU:STO
tAA SDA (OUTPUT TIMING)
tDH
tBUF
EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR VDD = 5V 5.0V 1533 SDA, IRQ AND FOUT 100pF FOR VOL= 0.4V AND IOL = 3mA
FIGURE 1. STANDARD OUTPUT LOAD FOR TESTING THE DEVICE WITH VDD = 5.0V
Symbol Table
WAVEFORM INPUTS Must be steady OUTPUTS Will be steady
May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed N/A
Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance
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FN6682.2 June 24, 2009
ISL12023 Typical Performance Curves Temperature is +25C unless otherwise specified.
1050 1000 IBAT (nA) 950 900 850 800 1.8 1600 1400 1200 1000 VBAT = 3.0V 800 VBAT = 1.8V 2.3 2.8 3.3 3.8 4.3 4.8 5.3 600 -40 -20 0 20 40 60 80
VBAT CURRENT (nA)
VBAT = 5.5V
VBAT VOLTAGE (V)
TEMPERATURE (C)
FIGURE 2. IBAT vs VBAT
FIGURE 3. IBAT vs TEMPERATURE
6
4.4 4.2
5 VBAT = 5.5V IDD1 (A) IDD1 (A) VDD = 2.7V 3 VDD = 3.3V -20 0 20 40 TEMPERATURE (C) 60 80 4
4.0 3.8 3.6 3.4 3.2
2 -40
3.0 2.7
3.2
3.7
4.2 VDD (V)
4.7
5.2
FIGURE 4. IDD1 vs TEMPERATURE
FIGURE 5. IDD1 vs VDD
6 SUPPLY CURRENT (A)
5.5 5.0 4.5 4.0 3.5 3.0 2.5 -40 FOUT = 1Hz and 64Hz FOUT = 32kHz
5 IDD (A)
VDD = 5.5V
4 VDD = 3.3V
3
VDD = 2.7V
2 0.01
0.1
1 10 100 1k FREQUENCY OUTPUT (Hz)
10k
100k
-20
0 20 40 TEMPERATURE (C)
60
80
FIGURE 6. FOUT vs IDD
FIGURE 7. IDD vs TEMPERATURE, 3 DIFFERENT FOUT
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FN6682.2 June 24, 2009
ISL12023 Typical Performance Curves Temperature is +25C unless otherwise specified. (Continued)
110 100 90 IDD (A) 80 70 60 50 40 -40 -20 0 20 40 60 80 VDD = 3.3V VDD = 5.5V IBAT (A) VBAT = 2.7V 110 100 90 80 70 60 50 40 30 20 -40 -20 0 20 40 TEMPERATURE (C) 60 80 VBAT = 3.0V VBAT = 1.8V VBAT = 5.5V
TEMPERATURE (C)
FIGURE 8. IDD WITH TSE = 1 vs TEMPERATURE
FIGURE 9. IBAT with TSE = 1, BTSE = 1 vs TEMPERATURE
General Description
The ISL12023 device is a low power real time clock (RTC) with embedded temperature sensors. It contains crystal frequency compensation circuitry over the operating temperature range, clock/calendar, power fail and low battery monitors, brownout indicator with separate low voltage reset pin (LVRST), 1 periodic or polled alarm, intelligent battery-backup switching and 128 Bytes of battery-backed user SRAM. The oscillator uses an external, low cost 32.768kHz crystal. The real time clock tracks time with separate registers for hours, minutes and seconds. The device has calendar registers for date, month, year and day of the week. The calendar is accurate through 2099, with automatic leap year correction. In addition, the ISL12023 could be programmed for automatic Daylight Savings Time (DST) adjustment by entering local DST information. The ISL12023's alarm can be set to any clock/calendar value for a match. For example, every minute, every Tuesday or at 5:23 a.m. on March 21. The alarm status is available by checking the Status Register, or the device can be configured to provide a hardware interrupt via the IRQ pin. There is a repeat mode for the alarm allowing a periodic interrupt every minute, every hour, every day, etc. The device also offers a backup power input pin. This VBAT pin allows the device to be backed up by battery or super capacitor with automatic switchover from VDD to VBAT. The ISL12023 device is specified for VDD = 2.7V to 5.5V and the clock/calendar portion of the device remains fully operational in battery-backup mode down to 1.8V (Standby Mode). The VBAT level is monitored and reported against preselected levels. The first report is registered when the VBAT level falls below 85% of nominal level, the second level is set for 75%. Battery levels are stored in PWR_VBAT registers. The ISL12023 offers a "Brownout" alarm once the VDD falls below a pre-selected trip level. This allows system Micro to save vital information to memory before complete power
loss. There are six VDD levels that could be selected for initiation of the Brownout alarm.
Pin Descriptions
X1, X2
The X1 and X2 pins are the input and output, respectively, of an inverting amplifier. An external 32.768kHz quartz crystal is used with the device to supply a timebase for the real time clock. Internal compensation circuitry with internal temperature sensor provides frequency corrections for selected popular crystals to 5ppm over the operating temperature range from -40C to +85C (see "Application Section" on page 24 for recommended crystal). The ISL12023 allows the user to input via I2C serial bus the temperature variation profile of an individual crystal. The oscillator compensation network can also be used to calibrate the initial crystal timing accuracy to less than 1ppm error at room temperature. The device can also be driven directly from a 32.768kHz source at pin X1.
X1 X2
FIGURE 10. RECOMMENDED CRYSTAL CONNECTION
VBAT
This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event that the VDD supply fails. The device will automatically switch to the VBAT input when VDD drops below a prescribed level. See the Battery Monitor parameter in the electrical spec table titled "DC Operating Characteristics-RTC" on page 3. This pin can be connected to a battery, a super capacitor or tied to ground if not used.
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ISL12023
IRQ (Interrupt Output)
This pin provides an interrupt signal output. This signal notifies a host processor that an alarm has occurred and requests action. It is an open drain active low output. Once triggered, the output will stay low until the Alarm status register bit is reset or, if the auto reset function is used, a read is performed to the status register.
Normal Mode (VDD) to Battery-Backup Mode (VBAT)
To transition from the VDD to VBAT mode, both of the following conditions must be met: Condition 1: VDD < VBAT - VBATHYS where VBATHYS 50mV Condition 2: VDD < VTRIP where VTRIP 2.2V
FOUT (Frequency Output)
This pin provides a clock signal which is related to the crystal frequency. The output frequency is user selectable and enabled via the I2C bus. It is an open drain output.
Serial Clock (SCL)
The SCL input is used to clock all serial data into and out of the device. The input buffer on this pin is always active (not gated). It is disabled when the backup power supply on the VBAT pin is activated to minimize power consumption.
Battery-Backup Mode (VBAT) to Normal Mode (VDD)
The ISL12023 device will switch from the VBAT to VDD mode when one of the following conditions occurs: Condition 1: VDD > VBAT + VBATHYS where VBATHYS 50mV
BATTERY-BACKUP MODE
Serial Data (SDA)
SDA is a bi-directional pin used to transfer data into and out of the device. It has an open drain output and may be ORed with other open drain or open collector outputs. The input buffer is always active (not gated) in normal mode. An open drain output requires the use of a pull-up resistor. The output circuitry controls the fall time of the output signal with the use of a slope controlled pull-down. The circuit is designed for 400kHz I2C interface speeds. It is disabled when the backup power supply on the VBAT pin is activated.
VDD VBAT VTRIP VTRIP
3.0V 2.2V
VTRIP + VTRIPHYS
VDD, GND
Chip power supply and ground pins. The device will operate with a power supply from VDD = 2.7V to 5.5VDC. A 0.1F capacitor is recommended on the VDD pin to ground.
FIGURE 11. BATTERY SWITCHOVER WHEN VBAT > VTRIP
LVRST (Low Voltage Reset)
This pin provides an interrupt signal output. This signal notifies a host processor that the VDD level has dropped below the pre-programmed level, normally 85% of nominal VDD. The brownout trip level is programmable via a control register. It is an open drain active low output.
VDD VTRIP VBAT VBAT - VBATHYS
BATTERY-BACKUP MODE
2.2V 1.8V VBAT + VBATHYS
Functional Description
Power Control Operation
The power control circuit accepts a VDD and a VBAT input. Many types of batteries can be used with Intersil RTC products. For example, 3.0V or 3.6V Lithium batteries are appropriate, and battery sizes are available that can power the ISL12023 for up to 10 years. Another option is to use a super capacitor for applications where VDD is interrupted for up to a month. See the "Application Section" on page 24 for more information.
FIGURE 12. BATTERY SWITCHOVER WHEN VBAT < VTRIP
Condition 2: VDD > VTRIP + VTRIPHYS where VTRIPHYS 30mV These power control situations are illustrated in Figures 11 and 12. The I2C bus is deactivated in battery-backup mode to reduce power consumption. Aside from this, all RTC functions are operational during battery-backup mode. Except for SCL and SDA, all the inputs and outputs of the ISL12023 are active during battery-backup mode unless disabled via the control register.
FN6682.2 June 24, 2009
9
ISL12023
The device Time Stamps the switchover from VDD to VBAT and VBAT to VDD, and the time is stored in tSV2B and tSB2V registers respectively. If multiple VDD power-down sequences occur before status is read, the earliest VDD to VBAT power-down time is stored and the most recent VBAT to VDD time is stored. Temperature conversion and compensation can be enabled in battery-backup mode. Bit BTSE in the BETA register controls this operation, as described in "BETA Register (BETA)" on page 17. The normal power switching of the ISL12023 is designed to switch into battery-backup mode only if the VDD power is lost. This will ensure that the device can accept a wide range of backup voltages from many types of sources while reliably switching into backup mode. Note that the ISL12023 is not guaranteed to operate with VBAT < 1.8V. If the battery voltage is expected to drop lower than this minimum, correct operation of the device, especially after a VDD power down cycle, is not guaranteed. The minimum VBAT to insure SRAM is stable is 1.0V. Below that, the SRAM may be corrupted when VDD power resumes.
Power Failure Detection
The ISL12023 provides a Real Time Clock Failure Bit (RTCF) to detect total power failure. It allows users to determine if the device has powered up after having lost all power to the device (both VDD and VBAT).
Real Time Clock Operation
The Real Time Clock (RTC) uses an external 32.768kHz quartz crystal to maintain an accurate internal representation of second, minute, hour, day of week, date, month, and year. The RTC also has leap-year correction. The clock also corrects for months having fewer than 31 days and has a bit that controls 24-hour or AM/PM format. When the ISL12023 powers up after the loss of both VDD and VBAT, the clock will not begin incrementing until at least one byte is written to the clock register.
Brownout Detection
The ISL12023 monitors the VDD level continuously and provides warning if the VDD level drops below prescribed levels. There are six (6) levels that can be selected for the trip level. These values are 85% below popular VDD levels. The LVDD bit in the Status Register will be set to "1" when brownout is detected. Note that the I2C serial bus remains active unless the Battery VTRIP levels are reached. The LVRST output becomes active (LOW) when the Power Brownout Bit (LVDD) is set. When the VDD power is re-established and is above the 85% VDD + 50mV trip point, the LVRST output is set HIGH. The LVDD bit is reset once it is read by the Micro. Note that the I2C serial bus remains active unless the Battery VTRIP levels are reached.
Single Event and Interrupt
The alarm mode is enabled via the MSB bit. Choosing single event or interrupt alarm mode is selected via the IM bit. Note that when the frequency output function is enabled, the alarm function is disabled. The standard alarm allows for alarms of time, date, day of the week, month, and year. When a time alarm occurs in single event mode, an IRQ pin will be pulled low and the alarm status bit (ALM) will be set to "1". The pulsed interrupt mode allows for repetitive or recurring alarm functionality. Hence, once the alarm is set, the device will continue to alarm for each occurring match of the alarm and present time. Thus, it will alarm as often as every minute (if only the nth second is set) or as infrequently as once a year (if at least the nth month is set). During pulsed interrupt mode, the IRQ pin will be pulled low for 250ms and the alarm status bit (ALM) will be set to "1". The ALM bit can be reset by the user or cleared automatically using the auto reset mode (see ARST bit). The alarm function can be enabled/disabled during battery-backup mode using the FOBATB bit. For more information on the alarm, please see "ALARM Registers (10h to 15h)" on page 19.
Battery Level Monitor
The ISL12023 has a built in warning feature once the backup battery level drops first to 85% and then to 75% of the battery's nominal VBAT level. When the battery voltage drops to between 85% and 75%, the LBAT85 bit is set in the status register. When the level drops below 75%, both LBAT85 and LBAT75 bits are set in the status register. The battery level monitor is not functional in battery backup mode. In order to read the monitor bits after powering up VDD, instigate a battery level measurement by setting the TSE bit to "1" (BETA register), and then read the bits. There is a Battery Time Stamp Function available. Once the VDD is low enough to enable switchover to the battery, the RTC time/date are written into the TSV2B register. This information can be read from the TSV2B registers to discover the point in time of the VDD power-down. If there are multiple power-down cycles before reading these registers, the first values stored in these registers will be retained. These registers will hold the original power-down value until they are cleared by setting CLRTS = 1 to clear the registers.
Frequency Output Mode
The ISL12023 has the option to provide a clock output signal using the FOUT open drain output pin. The frequency output mode is set by using the FO bits to select one of 15 possible output frequency values from 1/32Hz to 32kHz. The frequency output can be enabled/disabled during battery-backup mode using the FOBATB bit.
FN6682.2 June 24, 2009
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ISL12023
General Purpose User SRAM
The ISL12023 provides 128 bytes of user SRAM. The SRAM will continue to operate in battery-backup mode. However, it should be noted that the I2C bus is disabled in battery-backup mode. The registers are divided into 8 sections. They are: 1. Real Time Clock (7 bytes): Address 00h to 06h. 2. Control and Status (13 bytes): Address 07h to 0Fh and 2Ah to 2Dh. 3. Alarm (6 bytes): Address 10h to 15h. 4. Time Stamp for Battery Status (5 bytes): Address 16h to 1Ah. 5. Time Stamp for VDD Status (5 bytes): Address 1Bh to 1Fh. 6. Daylight Saving Time (8 bytes): 20h to 27h. 7. Temperature (2 bytes): 28h to 29h 8. Crystal Net PPM Correction, NPPM (2 bytes): 2Ah, 2Bh 9. Crystal Turnover Temperature, XT0 (1 byte): 2Ch 10. Crystal ALPHA at high temperature, ALPHA_H (1 byte): 2Dh 11. Scratch Pad (2 bytes): Address 2Eh and 2Fh Write capability is allowable into the RTC registers (00h to 06h) only when the WRTC bit (bit 6 of address 08h) is set to "1". A multi-byte read or write operation should be limited to one section per operation for best RTC time keeping performance. When the previous ddress is 2Fh, the next address will wrap around to 00h. A register can be read by performing a random read at any address at any time. This returns the contents of that register location. Additional registers are read by performing a sequential read. For the RTC and Alarm registers, the read instruction latches all clock registers into a buffer, so an update of the clock does not change the time being read. At the end of a read, the master supplies a stop condition to end the operation and free the bus. After a read, the address remains at the previous address +1 so the user can execute a current address read and continue reading the next register. It is not necessary to set the WRTC bit prior to writing into the control and status, alarm, and user SRAM registers.
I2C Serial Interface
The ISL12023 has an I2C serial bus interface that provides access to the control and status registers and the user SRAM. The I2C serial interface is compatible with other industry I2C serial bus protocols using a bi-directional data signal (SDA) and a clock signal (SCL).
Oscillator Compensation
The ISL12023 provides both initial timing correction and temperature correction due to variation of the crystal oscillator. Analog and digital trimming control is provided for initial adjustment, and a temperature compensation function is provided to automatically correct for temperature drift of the crystal. Initial values are preset and recalled on initial power-up for the Initial AT and DT settings (IATR, IDTR), temperature coefficient (ALPHA), crystal capacitance (BETA), and the crystal turnover temperature (XTO). These initial values are typical of units available on the market, although the user may program specific values after testing for best accuracy. The function can be enabled/disabled at any time and can be used in battery mode as well.
Register Descriptions
The battery-backed registers are accessible following a slave byte of "1101111x" and reads or writes to addresses [00h:2Fh]. The defined addresses and default values are described in the Table 1. The battery backed general purpose SRAM has a different slave address (1010111x), so it is not possible to read/write that section of memory while accessing the registers. REGISTER ACCESS The contents of the registers can be modified by performing a byte or a page write operation directly to any register address.
REG NAME SC MN HR RTC DT MO YR DW
TABLE 1. REGISTER MEMORY MAP BIT 7 0 0 MIL 0 0 YR23 0 6 SC22 MN22 0 0 0 YR22 0 5 SC21 MN21 HR21 DT21 0 YR21 0 4 SC20 MN20 HR20 DT20 MO20 YR20 0 3 SC13 MN13 HR13 DT13 MO13 YR13 0 2 SC12 MN12 HR12 DT12 MO12 YR12 DW2 1 SC11 MN11 HR11 DT11 MO11 YR11 DW1 0 SC10 MN10 HR10 DT10 MO10 YR10 DW0 RANGE 0 to 59 0 to 59 0 to 23 1 to 31 1 to 12 0 to 99 0 to 6 DEFAULT 00h 00h 00h 01h 01h 00h 00h
ADDR. SECTION 00h 01h 02h 03h 04h 05h 06h
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TABLE 1. REGISTER MEMORY MAP (Continued) REG NAME SR INT PWR_VDD PWR_VBAT CSR ITRO ALPHA BETA FATR FDTR SCA0 MNA0 HRA0 ALARM DTA0 MOA0 DWA0 VSC VMN TSV2B VHR VDT VMO BSC BMN TSB2V BHR BDT BMO DstMoFd DstDwFd DstDtFd DstHrFd DSTCR DstMoRv DstDwRv DstDtRv DstHrRv TK0L TEMP TK0M NPPML NPPM XT0 ALPHAH GPM NPPMH XT0 ALPHAH GPM1 GPM2 IDTR01 D TSE 0 0 ESCA0 EMNA0 EHRA0 EDTA0 EMOA00 EDWA0 0 0 VMIL 0 0 0 0 BMIL 0 0 DSTE D D D D D D D TK07 0 NPPM7 0 D D GPM17 GPM27 BIT 7 BUSY ARST CLRTS 6 OSCF WRTC D RESEALB IDTR00 ALPHA6 BTSE 0 0 SCA022 MNA022 D D D D VSC22 VMN22 0 0 0 BSC22 BMN22 0 0 0 D 5 DSTADJ IM D VB85Tp2 IATR05 ALPHA5 BTSR FFATR5 0 SCA021 MNA021 HRA021 DTA021 D D VSC21 VMN21 VHR21 VDT21 0 BSC21 BMN21 BHR21 BDT21 0 D 4 ALM FOBATB D VB85Tp1 IATR04 ALPHA4 BETA4 FATR4 FDTR4 SCA020 MNA020 HRA020 DTA020 MOA020 D VSC20 VMN20 VHR20 VDT20 VMO20 BSC20 BMN20 BHR20 BDT20 BMO20 3 LVDD FO3 D VB85Tp0 IATR03 ALPHA3 BETA3 FATR3 FDTR3 SCA013 MNA013 HRA013 DTA013 MOA013 D VSC13 VMN13 VHR13 VDT13 VMO13 BSC13 BMN13 BHR13 BDT13 BMO13 2 LBAT85 FO2 VDDTrip2 VB75Tp2 IATR02 ALPHA2 BETA2 FATR2 FDTR2 SCA012 MNA012 HRA012 DTA012 MOA012 DWA02 VSC12 VMN12 VHR12 VDT12 VMO12 BSC12 BMN12 BHR12 BDT12 BMO12 1 LBAT75 FO1 VDDTrip1 VB75Tp1 IATR01 ALPHA1 BETA1 FATR1 FDTR1 SCA011 MNA011 HRA011 DTA011 MOA011 DWA01 VSC11 VMN11 VHR11 VDT11 VMO11 BSC11 BMN11 BHR11 BDT11 BMO11 0 RTCF FO0 VDDTrip0 VB75Tp0 IATR00 ALPHA0 BETA0 FATR0 FDTR0 SCA010 MNA010 HRA010 DTA010 MOA010 DWA00 VSC10 VMN10 VHR10 VDT10 VMO10 BSC10 BMN10 BHR10 BDT10 BMO10 RANGE N/A N/A N/A N/A N/A N/A N/A N/A N/A 00 to 59 00 to 59 0 to 23 01 to 31 01 to 12 0 to 6 0 to 59 0 to 59 0 to 23 1 to 31 1 to 12 0 to 59 0 to 59 0 to 23 1 to 31 1 to 12 1 to 12 0 to 6 1 to 31 0 to 23 01 to 12 0 to 6 01 to 31 0 to 23 00 to FF 00 to 03 00 to FF 00 to 07 00 to FF 00 to 7F 00 to FF 00 to FF DEFAULT 01h 01h 00h 00h 20h 46h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 46h 00h 00h
ADDR. SECTION 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh
DstMoFd20 DstMoFd13 DstMoFd12 DstMoFd11 DstMoFd10
DstDwFdE DstWkFd12 DstWkFd11 DstWkFd10 DstDwFd12 DstDwFd11 DstDwFd10 D D D DstDtFd21 DstHrFd21 D DstDtFd20 DstHrFd20 DstDtFd13 DstDtFd12 DstDtFd11 DstDtFd10
DstHrFd13 DstHrFd12 DstHrFd11 DstHrFd10
XDstMoRv20 DstMoRv13 DstMoR12v DstMoRv11 DstMoRv10
DstDwRvE DstWkrv12 DstWkRv11 DstWkRv10 DstDwRv12 DstDwRv11 DstDwRv10 D D TK06 0 NPPM6 0 D ALP_H6 GPM16 GPM26 DstDtRv21 DstHrRv21 TK05 0 NPPM5 0 D ALP_H5 GPM15 GPM25 DstDtRv20 DstHrRv20 TK04 0 NPPM4 0 XT4 ALP_H4 GPM14 GPM24 DstDtRv13 DstDtRv12 DstDtRv11 DstDtRv10 DstHrRv13 DstHrRv12 DstHrRv11 DstHrRv10 TK03 0 NPPM3 0 XT3 ALP_H3 GPM13 GPM23 TK02 0 NPPM2 NPPM10 XT2 ALP_H2 GPM12 GPM22 TK01 TK09 NPPM1 NPPM9 XT1 ALP_H1 GPM11 GPM21 TK00 TK08 NPPM0 NPPM8 XT0 ALP_H0 GPM10 GPM20
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ISL12023 Real Time Clock Registers
Addresses [00h to 06h]
RTC REGISTERS (SC, MN, HR, DT, MO, YR, DW) These registers depict BCD representations of the time. As such, SC (Seconds) and MN (Minutes) range from 0 to 59, HR (Hour) can either be a 12-hour or 24-hour mode, DT (Date) is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99, and DW (Day of the Week) is 0 to 6. The DW register provides a Day of the Week status and uses three bits DW2 to DW0 to represent the seven days of the week. The counter advances in the cycle 0-1-2-3-4-5-6-0-12-... The assignment of a numerical value to a specific day of the week is arbitrary and may be decided by the system software designer. The default value is defined as "0". 24-HOUR TIME If the MIL bit of the HR register is "1", the RTC uses a 24-hour format. If the MIL bit is "0", the RTC uses a 12-hour format and HR21 bit functions as an AM/PM indicator with a "1" representing PM. The clock defaults to 12-hour format time with HR21 = "0". LEAP YEARS Leap years add the day February 29 and are defined as those years that are divisible by 4. Years divisible by 100 are not leap years, unless they are also divisible by 400. This means that the year 2000 is a leap year and the year 2100 is not. The ISL12023 does not correct for the leap year in the year 2100. DAYLIGHT SAVING TIME CHANGE BIT (DSTADJ) DSTADJ is the Daylight Savings Time Adjusted Bit. It indicates the daylight saving time forward adjustment has happened. If a DST Forward event happens, DSTADJ will be set to "1". The DSTADJ bit will stay high when DSTFD event happens, and will be reset to "0" when the DST Reverse event happens. DSTADJ can be set to "1" for instances where the RTC device is initialized during the DST Forward period. The DSTE bit must be enabled when the RTC time is more than one hour before the DST Forward or DST Reverse event time setting, or the DST event correction will not happen. DSTADJ is reset to "0" upon power up. It will reset to "0" when the DSTE bit in Register 15h is set to "0" (DST disabled), but no time adjustment will happen. ALARM BIT (ALM) This bits announces if the alarm matches the real time clock. If there is a match, the respective bit is set to "1". This bit can be manually reset to "0" by the user or automatically reset by enabling the auto-reset bit (see ARST bit). A write to this bit in the SR can only set it to "0", not "1". An alarm bit that is set by an alarm occurring during an SR read operation will remain set after the read operation is complete. LOW VDD INDICATOR BIT (LVDD) This bit indicates when VDD has dropped below the pre-selected trip level (Brownout Mode). The trip points for the brownout levels are selected by three bits: VDD Trip2, VDD Trip1 and VDD Trip0 in PWR_ VDD registers. The LVDD detection is only enabled in VDD mode and the detection happens in real time. The LVDD bit is set whenever the VDD has dropped below the pre-selected trip level, and self clears whenever the VDD is above the preselected trip level. LOW BATTERY INDICATOR 85% BIT (LBAT85) In Normal Mode (VDD), this bit indicates when the battery level has dropped below the pre-selected trip levels. The trip points are selected by three bits: VB85Tp2, VB85Tp1 and VB85Tp0 in the PWR_VBAT registers. The LBAT85 detection happens automatically once every minute when seconds register reaches 59. The detection can also be manually triggered by setting the TSE bit in BETA register to "1". The LBAT85 bit is set when the VBAT has dropped below the pre-selected trip level, and will self clear when the VBAT is above the pre-selected trip level at the next detection cycle either by manual or automatic trigger. In Battery Mode (VBAT), this bit indicates the device has entered into battery mode by polling once every 10 minutes. The LBAT85 detection happens automatically once when the minute register reaches x9h or x0h minutes.
Control and Status Registers (CSR)
Addresses [07h to 0Fh]
The Control and Status Registers consist of the Status Register, Interrupt and Alarm Register, Analog Trimming and Digital Trimming Registers.
Status Register (SR)
The Status Register is located in the memory map at address 07h. This is a volatile register that provides either control or status of RTC failure (RTCF), Battery Level Monitor (LBAT85, LBAT75), alarm trigger, Daylight Savings Time, crystal oscillator enable and temperature conversion in progress bit.
TABLE 2. STATUS REGISTER (SR) ADDR 07h 7 6 5 4 3 2 1 0
BUSY OSCF DSTDJ ALM LVDD LBAT85 LBAT75 RTCF
BUSY BIT (BUSY) Busy Bit indicates temperature sensing is in progress. In this mode, Alpha, Beta and ITRO registers are disabled and cannot be accessed. OSCILLATOR FAIL BIT (OSCF) The Oscillator Fail Bit indicates that the oscillator has stopped. 13
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Example - When the LBAT85 is Set To "1" In Battery Mode: The minute the register changes to 19h when the device is in battery mode, the LBAT85 is set to "1" the next time the device switches back to Normal Mode. Example - When the LBAT85 Remains at "0" In Battery Mode: If the device enters into battery mode after the minute register reaches 20h and switches back to Normal Mode before the minute register reaches 29h, then the LBAT85 bit will remain at "0" the next time the device switches back to Normal Mode. LOW BATTERY INDICATOR 75% BIT (LBAT75) In Normal Mode (VDD), this bit indicates when the battery level has dropped below the pre-selected trip levels. The trip points are selected by three bits: VB75Tp2, VB75Tp1 and VB75Tp0 in the PWR_VBAT registers. The LBAT75 detection happens automatically once every minute when seconds register reaches 59. The detection can also be manually triggered by setting the TSE bit in BETA register to "1". The LBAT75 bit is set when the VBAT has dropped below the pre-selected trip level, and will self clear when the VBAT is above the pre-selected trip level at the next detection cycle either by manual or automatic trigger. In Battery Mode (VBAT), this bit indicates the device has entered into battery mode by polling once every 10 minutes. The LBAT85 detection happens automatically once when the minute register reaches x9h or x0h minutes. Example - When the LBAT75 is Set to "1" in Battery Mode: The minute register changes to 30h when the device is in battery mode, the LBAT75 is set to "1" the next time the device switches back to Normal Mode. Example - When the LBAT75 Remains at "0" in Battery Mode: If the device enters into battery mode after the minute register reaches 49h and switches back to Normal Mode before minute register reaches 50h, then the LBAT75 bit will remain at "0" the next time the device switches back to Normal Mode. REAL TIME CLOCK FAIL BIT (RTCF) This bit is set to a "1" after a total power failure. This is a read only bit that is set by hardware (ISL12023 internally) when the device powers up after having lost all power (defined as VDD = 0V and VBAT = 0V). The bit is set regardless of whether VDD or VBAT is applied first. The loss of only one of the supplies does not set the RTCF bit to "1". The first valid write to the RTC section after a complete power failure resets the RTCF bit to "0" (writing one byte is sufficient). AUTOMATIC RESET BIT (ARST) This bit enables/disables the automatic reset of the ALM, LVDD, LBAT85, and LBAT75 status bits only. When ARST bit is set to "1", these status bits are reset to "0" after a valid read of the respective status register (with a valid STOP condition). When the ARST is cleared to "0", the user must manually reset the ALM, LVDD, LBAT85, and LBAT75 bits. WRITE RTC ENABLE BIT (WRTC) The WRTC bit enables or disables write capability into the RTC Timing Registers. The factory default setting of this bit is "0". Upon initialization or power up, the WRTC must be set to "1" to enable the RTC. Upon the completion of a valid write (STOP), the RTC starts counting. The RTC internal 1Hz signal is synchronized to the STOP condition during a valid write cycle. INTERRUPT/ALARM MODE BIT (IM) This bit enables/disables the interrupt mode of the alarm function. When the IM bit is set to "1", the alarm will operate in the interrupt mode, where an active low pulse width of 250ms will appear at the IRQ pin when the RTC is triggered by the alarm as defined by the alarm registers (0Ch to 11h). When the IM bit is cleared to "0", the alarm will operate in standard mode, where the IRQ pin will be set low until the ALM status bit is cleared to "0".
TABLE 4. IM BIT 0 1 INTERRUPT/ALARM FREQUENCY Single Time Event Set By Alarm Repetitive/Recurring Time Event Set By Alarm
FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB) This bit enables/disables the FOUT and IRQ pins during battery-backup mode (i.e. VBAT power source active). When the FOBATB is set to "1" the FOUT and IRQ pins are disabled during battery-backup mode. This means that both the frequency output and alarm output functions are disabled. When the FOBATB is cleared to "0", the FOUT and IRQ pins are enabled during battery-backup mode. Note that the open drain FOUT and IRQ pins will need a pullup to the battery voltage to operate in battery-backup mode. FREQUENCY OUT CONTROL BITS (FO<3:0>) These bits enable/disable the frequency output function and select the output frequency at the FOUT pin. See Table 5 for frequency selection.
TABLE 5. FREQUENCY SELECTION OF FOUT PIN FREQUENCY, FOUT UNITS 0 32768 Hz Hz Hz FO3 0 0 0 FO2 0 0 0 FO1 0 0 1 FO0 0 1 0
Interrupt Control Register (INT)
TABLE 3. INTERRUPT CONTROL REGISTER (INT) ADDR 08h 7 6 5 IM 4 3 2 1 0
4096
ARST WRTC
FOBATB FO3 FO2 FO1 FO0
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TABLE 5. FREQUENCY SELECTION OF FOUT PIN (Continued) FREQUENCY, FOUT UNITS 1024 64 32 16 8 4 2 1 1/2 1/4 1/8 1/16 1/32 Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz ADDR 7 FO3 0 0 0 0 0 1 1 1 1 1 1 1 1 FO2 0 1 1 1 1 0 0 0 0 1 1 1 1 FO1 1 0 0 1 1 0 0 1 1 0 0 1 1 FO0 1 0 1 0 1 0 1 0 1 0 1 0 1 0Ah 6 5 TABLE 7. 4 3 2 1 0 D RESEALB VB85Tp2 VB85Tp1 VB85Tp0 VB75Tp2 VB75Tp1 VB75Tp0
RESEAL BIT (RESEALB) This is the Reseal bit for actively disconnecting VBAT pin from the internal circuitry. Setting this bit allows the device to disconnect the battery and eliminate standby current drain while the device is unused. Once VDD is powered up, this bit is reset and the VBAT pin is then connected to the internal circuitry. BATTERY LEVEL MONITOR TRIP BITS (VB85TP<2:0>) Three bits selects the first alarm (85% of Nominal VBAT) level for the battery voltage monitor. There are total of 7 levels that could be selected for the first alarm. Any of the of levels could be selected as the first alarm with no reference as to nominal Battery voltage level. See Table 8.
TABLE 8. VB85T ALARM LEVEL BATTERY ALARM TRIP LEVEL (V) 2.125 2.295 2.550 2.805 3.060 4.250 4.675
POWER SUPPLY CONTROL REGISTER (PWR_VDD) Clear Time Stamp Bit (CLRTS)
ADDR 09h 7 CLRTS 6 0 5 0 4 0 3 0 2 1 0 VB85Tp2 0 0 0 0 1 1 1 VDDTrip2 VDDTrip1 VDDTrip0 VB85Tp1 0 0 1 1 0 0 1 VB85Tp0 0 1 0 1 0 1 0
This bit clears Time Stamp VDD to Battery (TSV2B) and Time Stamp Battery to VDD Registers (TSB2V). The default setting is 0 (CLRTS = 0) and the Enabled setting is 1 (CLRTS = 1)
VDD Brownout Trip Voltage BITS (VDDTrip<2:0>)
These bits set the 6 trip levels for the VDD alarm, indicating that VDD has dropped below a preset level. In this event, the LVDD bit in the Status Register is set to "1" and the LVRST pin is asserted LOW. See Table 6.
TABLE 6. VDD TRIP LEVELS TRIP VOLTAGE (V) 2.295 2.550 2.805 3.060 4.250 4.675
BATTERY LEVEL MONITOR TRIP BITS (VB75TP<2:0>) Three bits select the second alarm (75% of Nominal VBAT) level for the battery voltage monitor. There are total of 7 levels that could be selected for the second alarm. Any of the of levels could be selected as the second alarm with no reference as to nominal Battery voltage level. See Table 9.
TABLE 9. BATTERY LEVEL MONITOR TRIP BITS (VB75TP<2:0>) BATTERY ALARM TRIP LEVEL (V) 1.875 2.025 2.250 2.475 2.700 3.750 4.125
VDDTrip2 0 0 0 0 1 1
VDDTrip1 0 0 1 1 0 0
VDDTrip0 0 1 0 1 0 1
VB75Tp2 0 0 0 0 1 1 1
VB75Tp1 0 0 1 1 0 0 1
VB75Tp0 0 1 0 1 0 1 0
Battery Voltage Trip Voltage Register (PWR_VBAT)
This register controls the trip points for the two VBAT alarms, with levels set to approximately 85% and 75% of the nominal battery level.
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Initial AT and DT Setting Register (ITRO)
These bits are used to trim the initial error (at room temperature) of the crystal. Both Digital Trimming (DT) and Analog Trimming (AT) methods are available. The digital trimming uses clock pulse skipping and insertion for frequency adjustment. Analog trimming uses load capacitance adjustment to pull the oscillator frequency. A range of +62.5ppm to -61.5ppm is possible with combined digital and analog trimming. AGING AND INITIAL TRIM DIGITAL TRIMMING BITS (IDTR0<1:0>) These bits allow 30.5ppm initial trimming range for the crystal frequency. This is meant to be a coarse adjustment if the range needed is outside that of the IATR control. See Table 10. The IDTR0 register should only be changed while the TSE (Temp Sense Enable) bit is "0".
TABLE 10. IDTR0 TRIMMING RANGE IDTR01 0 0 1 1 IDTR00 0 1 0 1 TRIMMING RANGE Default/Disabled +30.5ppm 0ppm -30.5ppm TABLE 12. IATRO TRIMMING RANGE (Continued) IATR05 IATR04 IATR03 IATR02 IATR01 IATR00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 TRIMMING RANGE +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 -23 -24 -25 -26 -27
AGING AND INITIAL ANALOG TRIMMING BITS (IATR0<5:0>) The analog trimming register allows +32ppm to -31ppm adjustment in 1ppm/bit increments. This enables fine frequency adjustment for trimming initial crystal accuracy error or to correct for aging drift. The IATR0 register should only be changed while the TSE (Temp Sense Enable) bit is "0".
TABLE 11. INITIAL AT AND DT SETTING REGISTER ADDR 0Bh 7 6 5 4 3 2 1
IDTR01 IDTR00 IATR05 IATR04 IATR03 IATR02 IATR01 IATR00
Note that setting the IATR to the lowest settings (-31ppm) with the default 32kHz output can cause the oscillator frequency to become unstable on power-up. The lowest settings for IATR should be avoided to insure oscillator frequency integrity.
TABLE 12. IATRO TRIMMING RANGE TRIMMING IATR05 IATR04 IATR03 IATR02 IATR01 IATR00 RANGE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 +32 +31 +30 +29 +28 +27 +26 +25
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TABLE 12. IATRO TRIMMING RANGE (Continued) IATR05 IATR04 IATR03 IATR02 IATR01 IATR00 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 TRIMMING RANGE -28 -29 -30 -31
TEMP SENSOR CONVERSION IN BATTERY MODE BIT (BTSE) This bit enables the Temperature Sensing and Correction in battery mode. BTSE = 0 (default) no conversion, Temp Sensing or Compensation in battery mode. BTSE = 1 indicates Temp Sensing and Compensation enabled in battery mode. The BTSE is disabled when the battery voltage is lower than 2.7V. No temperature compensation will take place with VBAT<2.7V. FREQUENCY OF TEMPERATURE SENSING AND CORRECTION BIT (BTSR)
ALPHA Register (ALPHA)
TABLE 13. ALPHA REGISTER ADDR 0Ch 7 D 6 5 4 3 2 1 0
ALPHA6 ALPHA5 ALPHA4 ALPHA3 ALPHA2 ALPHA1 ALPHA0
The Alpha variable is 8 bits and is defined as the temperature coefficient of Crystal from -40C to T0, or the Alpha Cold (there is an Alpha Hot register that must be programmed as well). It is normally given in units of ppm/C2, with a typical value of -0.034. The ISL12023 device uses a scaled version of the absolute value of this coefficient in order to get an integer value. Therefore, Alpha<7:0> is defined as the (|Actual Alpha Value| x 2048) and converted to binary. For example, a crystal with Alpha of -0.034ppm/C2 is first scaled (|2048*(-0.034)| = 70d) and then converted to a binary number of 01000110b. The practical range of Actual Alpha values is from -0.020 to -0.060. The ALPHA register should only be changed while the TSE (Temp Sense Enable) bit is "0". Note that both the ALPHA and the ALPHA Hot registers need to be programmed with values for full range temperature compensation.
This bit controls the frequency of Temp Sensing and Correction. BTSR = 0 default mode is every 10 minutes, BTSR = 1 is every 1.0 minute. Note that BTSE has to be enabled in both cases. See Table 15.
TABLE 15. FREQUENCY OF TEMPERATURE SENSING AND CORRECTION BIT BTSE 0 0 1 1 BTSR 0 1 0 1 TC PERIOD IN BATTERY MODE OFF OFF 10 Minutes 1 Minute
The temperature measurement conversion time is the same for battery mode as for VDD mode, approximately 22ms. The battery mode current will increase during this conversion time to typically 68A. The average increase in battery current is much lower than this due to the small duty cycle of the ON-time versus OFF-time for the conversion. To figure the average increase in battery current, we take the the change in current times the duty cycle. For the 1 minute temperature period the average current is shown in Equation 1:
BETA Register (BETA)
TABLE 14. ADDR 0Dh 7 6 5 4 3 2 1 0
0.022s I BAT = ----------------- x 68A = 250nA 60s
(EQ. 1)
TSE BTSE BTSR BETA4 BETA3 BETA2 BETA1 BETA0
For the 10 minute temperature period the average current is shown in Equation 2:
0.022s I BAT = ----------------- x 68A = 25nA 600s (EQ. 2)
TEMPERATURE SENSOR ENABLED BIT (TSE) This bit enables the Temperature Sensing operation, including the temperature sensor, A/D converter and AT/DT register adjustment. The default mode after power-up is disabled (TSE = 0). To enable the operation, TSE should be set to 1 (TSE = 1). When temperature sense is disabled, the initial values for IATR and IDTR registers are used for frequency control. All changes to the IDTR, IATR, ALPHA and BETA registers must be made with TSE = 0. After loading the new values, TSE can be enabled and the new values are used. When TSE is set to 1, the temperature conversion cycle begins and will end when two temperature conversions are completed. The average of the two conversions is in the TEMP registers.
If the application has a stable temperature environment that doesn't change quickly, the 10 minute option will work well and the backup battery lifetime impact is minimized. If quick temperature variations are expected (multiple cycles of more than 10 within an hour), then the 1 minute option should be considered and the slightly higher battery current figured into overall battery life. GAIN FACTOR OF AT BIT (BETA<4:0>) Beta is specified to take care of the Cm variations of the crystal. Most crystals specify Cm around 2.2fF. For example, if Cm > 2.2fF, the actual AT steps may reduce from 1ppm/step to approximately 0.80ppm/step. Beta is then used to adjust for this variation and restore the step size to 1ppm/step.
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BETA values are limited in the range from 01000 to 11111 as shown in Table 16. To use Table 16, the device is tested at two AT settings as follows: BETA VALUES = (AT(max) - AT(min))/63, where: AT(max) = FOUT in ppm (at AT = 00H) and AT(min) = FOUT in ppm (at AT = 3FH). The BETA VALUES result is indexed in the right hand column and the resulting Beta factor (for the register) is in the same row in the left column. The value for BETA should only be changed while the TSE (Temp Sense Enable) bit is "0". The procedure for writing the BETA register involves two steps. First, write the new value of BETA with TSE = 0. Then write the same value of BETA with TSE = 1. This will insure the next temp sense cycle will use the new BETA value.
TABLE 16. BETA VALUES BETA<4:0> 01000 00111 00110 00101 00100 00011 00010 00001 00000 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 AT STEP ADJUSTMENT 0.5000 0.5625 0.6250 0.6875 0.7500 0.8125 0.8750 0.9375 00010 1.0000 1.0625 1.1250 1.1875 1.2500 1.3125 1.3750 1.4375 1.5000 1.5625 1.6250 1.6875 1.7500 1.8125 1.8750 10111 1.9375 2.0000 11000 11001 11010 -7 -8 -9 -10 -213.5 -244 -274.5 -305 00011 00100 00101 00110 00111 01000 01001 01010 10000 10001 10010 10011 10100 10101 10110 2 3 4 5 6 7 8 9 10 0 -1 -2 -3 -4 -5 -6 61 91.5 122 152.5 183 213.5 244 274.5 305 0 -30.5 -61 -91.5 -122 -152.5 -183 FDTR<2:0> 00000 00001 DECIMAL 0 1
Final Analog Trimming Register (FATR)
This register shows the final setting of AT after temperature correction. It is read-only, the user cannot overwrite a value to this register. This value is accessible as a means of monitoring the temperature compensation function. See Table 17.
TABLE 17. FINAL ANALOG TRIMMING REGISTER ADDR 0Eh 7 0 6 0 5 4 3 2 1 0
FATR5 FATR4 FATR3 FATR2 FATR1 FATR0
Final Digital Trimming Register (FDTR)
This register shows the final setting of DT after temperature correction. It is read-only; the user cannot overwrite a value to this register. The value is accessible as a means of monitoring the temperature compensation function. The corresponding clock adjustment values are shown in Table 19. The DT setting has both positive and negative settings to adjust for any offset in the crystal.
.
TABLE 18. FINAL DIGITAL TRIMMING REGISTER ADDR 0Fh 7 0 6 0 5 0 4 3 2 1 0
FDTR4 FDTR3 FDTR2 FDTR1 FDTR0
TABLE 19. CLOCK ADJUSTMENT VALUES FOR FINAL DIGITAL TRIMMING REGISTER ADJUSTMENT (ppm) 0 30.5
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ALARM Registers (10h to 15h)
The alarm register bytes are set up identical to the RTC register bytes, except that the MSB of each byte functions as an enable bit (enable = "1"). These enable bits specify which alarm registers (seconds, minutes, etc.) are used to make the comparison. Note that there is no alarm byte for year. The alarm function works as a comparison between the alarm registers and the RTC registers. As the RTC advances, the alarm will be triggered once a match occurs between the alarm registers and the RTC registers. Any one alarm register, multiple registers, or all registers can be enabled for a match. There are two alarm operation modes: Single Event and periodic Interrupt Mode: * Single Event Mode is enabled by setting the bit 7 on any of the Alarm registers (ESCA0... EDWA0) to "1", the IM bit to "0", and disabling the frequency output. This mode permits a one-time match between the Alarm registers and the RTC registers. Once this match occurs, the ALM bit is set to "1" and the IRQ output will be pulled low and will remain low until the ALM bit is reset. This can be done manually or by using the auto-reset feature. * Interrupt Mode is enabled by setting the bit 7 on any of the Alarm registers (ESCA0... EDWA0) to "1", the IM bit to "1", and disabling the frequency output. The IRQ output will now be pulsed each time an alarm occurs. This means that once the interrupt mode alarm is set, it will continue to alarm for each occurring match of the alarm and present time. This mode is convenient for hourly or daily hardware interrupts in microcontroller applications such as security cameras or utility meter reading. To clear a single event alarm, the ALM bit in the status register must be set to "0" with a write. Note that if the ARST bit is set to 1 (address 08h, bit 7), the ALM bit will automatically be cleared when the status register is read. Following are examples of both Single Event and periodic Interrupt Mode alarms. Example 1 * Alarm set with single interrupt (IM = "0") * A single alarm will occur on January 1 at 11:30 a.m. * Set Alarm registers as follows:
BIT ALARM REGISTER 7 6 5 4 3 2 1 0 HEX SCA0 MNA0 HRA0 DTA0 MOA0 DWA0
After these registers are set, an alarm will be generated when the RTC advances to exactly 11:30 a.m. on January 1 (after seconds changes from 59 to 00) by setting the ALM bit in the status register to "1" and also bringing the IRQ output low. Example 2 * Pulsed interrupt once per minute (IM = "1") * Interrupts at one minute intervals when the seconds register is at 30s. * Set Alarm registers as follows:
BIT ALARM REGISTER 7 6 5 4 3 2 1 0 HEX SCA0 MNA0 HRA0 DTA0 MOA0 DWA0
DESCRIPTION
1 0 1 1 0 0 0 0 B0h Seconds set to 30, enabled 0 0 0 0 0 0 0 0 00h Minutes disabled 0 0 0 0 0 0 0 0 00h Hours disabled 0 0 0 0 0 0 0 0 00h Date disabled 0 0 0 0 0 0 0 0 00h Month disabled 0 0 0 0 0 0 0 0 00h Day of week disabled
Once the registers are set, the following waveform will be seen at IRQ:
RTC AND ALARM REGISTERS ARE BOTH "30s"
60s
FIGURE 13. IRQ WAVEFORM
Note that the status register ALM bit will be set each time the alarm is triggered, but does not need to be read or cleared.
Time Stamp VDD to Battery Registers (TSV2B)
The TSV2B Register bytes are identical to the RTC register bytes, except they do not extend beyond the Month. The Time Stamp captures the FIRST VDD to Battery Voltage transition time, and will not update upon subsequent events, until cleared (only the first event is captured before clearing). Set CLRTS = 1 to clear this register (Add 09h, PWR_VDD register). Note that the time stamp registers are cleared to all "0", including the month and day, which is different from the RTC and alarm registers (those registers default to 01h). This is the indicator that no time stamping has occurred since the last clear or initial power-up. Once a time stamp occurs, there will be a non-zero time stamp.
DESCRIPTION
0 0 0 0 0 0 0 0 00h Seconds disabled 1 0 1 1 0 0 0 0 B0h Minutes set to 30, enabled 1 0 0 1 0 0 0 1 91h Hours set to 11, enabled 1 0 0 0 0 0 0 1 81h Date set to 1, enabled 1 0 0 0 0 0 0 1 81h Month set to 1, enabled 0 0 0 0 0 0 0 0 00h Day of week disabled
Time Stamp Battery to VDD Registers (TSB2V)
The Time Stamp Battery to VDD Register bytes are identical to the RTC register bytes, except they do not extend beyond Month. The Time Stamp captures the LAST transition of VBAT to VD (only the last event of a series of power-up/down
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events is retained). Set CLRTS = 1 to clear this register (add 09h, PWR_VDD register). Day/Week is the priority. You must have the correct Day of Week entered in the RTC registers for the Day/Week correction to work properly. * Bits 0, 1, 2 contain the Day of the week information which sets the Day of the Week that DST starts. Note that Day of the week counts from 0 to 6, like the RTC registers. The default for the DST Forward Day of the Week is 00h (normally Sunday). * Bits 3, 4, 5 contain the Week of the Month information that sets the week that DST starts. The range is from 1 to 5, and Week 7 is used to indicate the last week of the month. The default for the DST Forward Week of the Month is 00h. DST Date Forward DstDtfd controls which Date DST begins. The format for the Date is the same as for the RTC register, from 1 to 31. The default value for DST forward date is 00h. DstDtFd is only effective if DstDwFdE = 0. DST Hour Forward DstHrFd controls the hour that DST begins. The RTC hour and DstHrFd registers have the same formats except there is no Military bit for DST hour. The user sets the DST hour with the same format as used for the RTC hour (AM/PM or MIL) but without the MIL bit, and the DST will still advance as if the MIL bit were there. The default value for DST hour Forward is 00h. DST REVERSE REGISTERS (24H TO 27H) DST end (reverse) is controlled by the following DST Registers: DST Day/Week Forward DstDwFd contains both the Day of the Week and the Week of the Month data for DST Forward control. DST can be controlled either by actual date or by setting both the Week of the month and the Day of the Week. DstDwFdE sets the priority of the Day/Week over the Date. For DstDwFdE = 1, DST Month Reverse DstMoRv sets the Month that DST ends. The format is the same as for the RTC register month, from 1 to 12. The default value for the DST end month is October (10h).
DST Control Registers (DSTCR)
8 bytes of control registers have been assigned for the Daylight Savings Time (DST) functions. DST beginning (set Forward) time is controlled by the registers DstMoFd, DstDwFd, DstDtFd, and DstHrFd. DST ending time (set Backward or Reverse) is controlled by DstMoRv, DstDwRv, DstDtRv and DstHrRv. Tables 20 and 21 describe the structure and functions of the DSTCR. DST FORWARD REGISTERS (20H TO 23H) DST forward is controlled by the following DST Registers: DST Enable DSTE is the DST Enabling Bit located in bit 7 of register 20h (DstMoFdxx). Set DSTE = 1 will enable the DSTE function. Upon powering up for the first time (including battery), the DSTE bit defaults to "0". When DSTE is set to "1" the RTC time must be at least one hour before the scheduled DST time change for the correction to take place. When DSTE is set to "0", the DSTADJ bit in the Status Register automatically resets to "0". DST Month Forward DstMoFd sets the Month that DST starts. The format is the same as for the RTC register month, from 1 to 12. The default value for the DST begin month is 00h.
TABLE 20. DST FORWARD REGISTERS ADDRESS 20h 21h 22h 23h FUNCTION Month Forward Day Forward Date Forward Hour Forward 7 DSTE 0 0 0 6 0 DwFdE 0 0 5 0 WkFd12 DtFd21 HrFd21 4 MoFd20 WkFd11 DtFd20 HrFd20 3 MoFd13 WkFd10 DtFd13 HrFd13 2 MoFd12 DwFd12 DtFd12 HrFd12 1 MoFd11 DwFd11 DtFd11 HrFd11 0 MoFd10 DwFd10 DtFd10 HrFd10
TABLE 21. DST REVERSE REGISTERS ADDRESS 24h 25h 26h 27h NAME Month Reverse Day Reverse Date Reverse Hour Reverse 7 0 0 0 0 6 0 DwRvE 0 0 5 0 WkRv12 DtRv21 HrRv21 4 MoRv20 WkRv11 DtRv20 HrRv20 3 MoRv13 WkRv10 DtRv13 HrRv13 2 MoRv12 DwRv12 DtRv12 HrRv12 1 MoRv11 DwRv11 DtRv11 HrRv11 0 MoRv10 DwRv10 DtRv10 HrRv10
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DST Day/Week Reverse DstDwRv contains both the Day of the Week and the Week of the Month data for DST Reverse control. DST can be controlled either by actual date or by setting both the Week of the month and the Day of the Week. DstDwRvE sets the priority of the Day/Week over the Date. For DstDwRvE = 1, Day/Week is the priority. You must have the correct Day of Week entered in the RTC registers for the Day/Week correction to work properly. * Bits 0, 1, 2 contain the Day of the week information which sets the Day of the Week that DST ends. Note that Day of the week counts from 0 to 6, like the RTC registers. The default for the DST Reverse Day of the Week is 00h (normally Sunday). * Bits 3, 4, 5 contain the Week of the Month information that sets the week that DST ends. The range is from 1 to 5, and Week 7 is used to indicate the last week of the month. The default for the DST Reverse Week of the Month is 00h. DST Date Reverse DstDtRv controls which Date DST ends. The format for the Date is the same as for the RTC register, from 1 to 31. The default value for DST Date Reverse is 00h. The DstDtRv is only effective if the DwRvE = 0. DST Hour Reverse DstHrRv controls the hour that DST ends. The RTC hour and DstHrFd registers have the same formats except there is no Military bit for DST hour. The user sets the DST hour with the same format as used for the RTC hour (AM/PM or MIL) but without the MIL bit, and the DST will still advance as if the MIL bit were there. The default value for DST hour Reverse is 00h
NPPM Registers (NPPM)
The NPPM value is exactly 2x the net correction required to bring the oscillator to 0ppm error. The value is the combination of oscillator Initial Correction (IPPM) and crystal temperature dependent correction (CPPM). IPPM is used to compensate the oscillator offset at room temperature and is controlled by the ITR0 and BETA registers, which are fixed during factor test. The CPPM compensates the oscillator frequency fluctuation over temperature. It is determined by the temperature (T), crystal curvature parameter (ALPHA), and crystal turnover temperature (XT0). T is the result of the temp sensor/ADC conversion, whose decimal result is 2x the actual temperature in Kelvin. ALPHA is from either the ALPHA (cold) or ALPHAH (hot) register depending on T, and XT0 is from the XT0 register. NPPM is governed by Equation 4: NPPM = IPPM(ITR0,BETA) + ALPHA x (T-T0)2
NPPM = IPPM + CPPM ALPHA * ( T - T0 ) NPPM = IPPM + --------------------------------------------------4096
2
(EQ. 4)
where:
ALPHA = * 2048
T is the reading of the ADC, result is 2 x temperature in degrees Kelvin.
T = ( 2 * 298 ) + XT0 (EQ. 5)
or T = 596 + XT0 Note that NPPM can also be predicted from the FATR and FDTR register by the relationship (all values in decimal): NPPM = 2*(BETA*FATR - (FDTR-16))
TEMP Registers (TEMP)
The temperature sensor produces an analog voltage output which is input to an A/D converter and produces a 10-bit temperature value in degrees Kelvin. TK07:00 are the LSBs of the code, and TK09:08 are the MSBs of the code. The temperature result is actually the average of two successive temperature measurements to produce greater resolution for the temperature control. The output code can be converted to degrees Centigrade (C) by first converting from binary to decimal, dividing by 2, and then subtracting 273d, as shown in Equation 3.
Temperature in C = [(TK <9:0>)/2] - 273 (EQ. 3)
XT0 Registers (XT0)
TURNOVER TEMPERATURE (XT<3:0>) The apex of the Alpha curve occurs at a point called the turnover temperature, or XT0. Crystals normally have a turnover temperature between +20C and +30C, with most occurring near +25C.
TABLE 23. TURNOVER TEMPERATURE ADDR 2Ch 7 0 6 0 5 0 4 XT4 3 XT3 2 XT2 1 XT1 0 XT0
The practical range for the temp sensor register output is from 446d to 726d, or -50C to +90C. The temperature compensation function is only guaranteed over -40C to +85C. The TSE bit must be set to "1" to enable temperature sensing.
TABLE 22. TEMP TK0L TK0M 7 6 5 4 3 2 1 0
The ISL12023 has a preset turnover temperature corresponding to the crystal in the module. This value is recalled on initial power-up and should never be changed for best temperature compensation performance, although the user may override this preset value if so desired. Table 24 shows the values available, with a range from +17.5C to +32.5C in +0.5C increments. The default value is 00000b or +25C.
TK07 TK06 TK05 TK04 TK03 TK02 TK01 TK00 0 0 0 0 0 0 TK09 TK08
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TABLE 24. XT0 VALUES XT<4:0> 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 TURNOVER TEMPERATURE 32.5 32.0 31.5 31 30.5 30 29.5 29.0 28.5 28.0 27.5 27.0 26.5 26.0 25.5 25.0 25.0 24.5 24.0 23.5 23.0 22.5 22.0 21.5 21.0 20.5 20.0 19.5 19.0 18.5 18.0 17.5
given in units of ppm/C2, with a typical value of -0.034. Like the ALPHA Cold version, a scaled version of the absolute value of this coefficient is used in order to get an integer value. Therefore, ALP_H<7:0> is defined as the (|Actual Alpha Hot Value| x 2048) and converted to binary. For example, a crystal with Alpha Hot of -0.034ppm/C2 is first scaled (|2048*(-0.034)| = 70d) and then converted to a binary number of 01000110b. The practical range of Actual ALPHAH values is from -0.020 to -0.060. The ISL12023 has a preset ALPHAH value corresponding to the crystal in the module. This value is recalled on initial power-up and should never be changed for best temperature compensation performance, although the user may override this preset value if so desired. The ALPHAH register should only be changed while the TSE (Temp Sense Enable) bit is "0".
User Registers (Accessed by Using Slave Address 1010111x)
Addresses [00h to 7Fh]
These registers are 128 bytes of battery-backed user SRAM. The separate I2C slave address must be used to read and write to these registers.
I2C Serial Interface
The ISL12023 supports a bi-directional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is the master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL12023 operates as a slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (see Figure 14). On power-up of the ISL12023, the SDA pin is in the input mode. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL12023 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (see Figure 14). A START condition is ignored during the power-up sequence. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 14). A STOP condition at the end
ALPHA Hot Register (ALPHAH)
TABLE 25. ALPHAH REGISTER
ADDR 2Dh 7 6 5 4 3 2 1 0
D
ALP_H6 ALP_H5 ALP_H4 ALP_H3 ALP_H2 ALP_H1 ALP_H0
The ALPHA Hot variable is 7 bits and is defined as the temperature coefficient of Crystal from the XT0 value to +85C (both Alpha Hot and Alpha Cold must be programmed to provide full temperature compensation). It is normally 22
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of a read operation or at the end of a write operation to memory only places the device in its standby mode. An acknowledge (ACK) is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting 8 bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the 8 bits of data (see Figure 15). The ISL12023 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL12023 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation.
Device Addressing
Following a start condition, the master must output a Slave Address Byte. The 7 MSBs are the device identifier. These bits are "1101111" for the RTC registers and 1010111" for the User SRAM. The last bit of the Slave Address Byte defines a read or write operation to be performed. When this R/W bit is a "1", then a read operation is selected. A "0" selects a write operation (refer to Figure 17).
SCL
SDA DATA STABLE DATA CHANGE DATA STABLE
START
STOP
FIGURE 14. VALID DATA CHANGES, START AND STOP CONDITIONS
SCL FROM MASTER
1
8
9
SDA OUTPUT FROM TRANSMITTER
HIGH IMPEDANCE
SDA OUTPUT FROM RECEIVER
HIGH IMPEDANCE
START
ACK
FIGURE 15. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE SIGNALS FROM THE MASTER S T A R T S T O P
IDENTIFICATION BYTE
ADDRESS BYTE
DATA BYTE
SIGNAL AT SDA SIGNALS FROM THE ISL12023
11011110 A C K
0000 A C K A C K
FIGURE 16. BYTE WRITE SEQUENCE (SLAVE ADDRESS FOR CSR SHOWN)
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.
1
1
0
1
1
1
1
R/W
SLAVE ADDRESS BYTE
responds with an ACK during the SCL cycle following the eighth bit of each byte. The master terminates the read operation (issuing a STOP condition) following the last bit of the last Data Byte (see Figure 18). The Data Bytes are from the memory location indicated by an internal pointer. This pointers initial value is determined by the Address Byte in the Read operation instruction, and increments by one during transmission of each Data Byte. After reaching the memory location 2Fh, the pointer "rolls over" to 00h, and the device continues to output data for each ACK received.
A7
A6
A5
A4
A3
A2
A1
A0
WORD ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
DATA BYTE
FIGURE 17. SLAVE ADDRESS, WORD ADDRESS, AND DATA BYTES
After loading the entire Slave Address Byte from the SDA bus, the ISL12023 compares the device identifier and device select bits with "1101111" or "1010111". Upon a correct compare, the device outputs an acknowledge on the SDA line. Following the Slave Byte is a one byte word address. The word address is either supplied by the master device or obtained from an internal counter. On power-up, the internal address counter is set to address 00h, so a current address read starts at address 00h. When required, as part of a random read, the master must supply the 1 Word Address Bytes, as shown in Figure 18. In a random read operation, the slave byte in the "dummy write" portion must match the slave byte in the "read" section. For a random read of the Control/Status Registers, the slave byte must be "1101111x" in both places.
Application Section
Battery-Backup Details
The ISL12023 has automatic switchover to battery-backup when the VDD drops below the VBAT mode threshold. A wide variety of backup sources can be used, including standard and rechargeable lithium, super capacitors, or regulated secondary sources. The serial interface is disabled in battery-backup, while the oscillator and RTC registers are operational. The SRAM register contents are powered to preserve their contents as well. The input voltage range for VBAT is 1.8V to 5.5V, but keep in mind the temperature compensation only operates for VBAT > 2.7V. Note that the device is not guaranteed to operate with a VBAT < 1.8V, so the battery should be changed before discharging to that level. It is strongly advised to monitor the low battery indicators in the status registers and take action to replace discharged batteries. If a supercapacitor is used, it is possible that it may discharge to below 1.8V during prolonged power-down. Once powered up, the device may lose serial bus communications until both VDD and VBAT are powered down together. To avoid that situation, including situations where a battery may discharge deeply, the circuit in Figure 19 can be used. Some applications will require separate supplies for the RTC VDD and the I2C pull-ups. This is not advised, as it may compromise the operation of the I2C bus. For applications that do require serial bus communication with the RTC VDD powered down, the SDA pin must be pulled low during the time the RTC VDD ramps down to 0V.
Write Operation
A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL12023 responds with an ACK. At this time, the I2C interface enters a standby state.
Read Operation
A Read operation consists of a three byte instruction followed by one or more Data Bytes (see Figure 18). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to "0", an Address Byte, a second START, and a second Identification byte with the R/W bit set to "1". After each of the three bytes, the ISL12023 responds with an ACK. Then the ISL12023 transmits Data Bytes as long as the master
SIGNALS FROM THE MASTER S T A R T
IDENTIFICATION BYTE WITH R/W = 0
ADDRESS BYTE
S T IDENTIFICATION A BYTE WITH R R/W = 1 T
A C K
A C K
S T O P
SIGNAL AT SDA SIGNALS FROM THE SLAVE
11011110 A C K A C K
11011111 A C K
FIRST READ DATA BYTE
LAST READ DATA BYTE
FIGURE 18. READ SEQUENCE (CSR SLAVE ADDRESS SHOWN)
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Otherwise, the device may lose serial bus communications once VDD is powered up, and will return to normal operation ONLY once VDD and VBAT are both powered down together.
VDD = 2.7V TO 5.5V CIN 0.1F GND ISL12023 VDD VBAT CBAT 0.1F JBAT DBAT BAT43W + VBAT = 1.8V TO 3.2V
clock or data lines. Careful layout of the RTC circuit will avoid noise pickup and insure accurate clocking. Figure 20 shows a suggested layout for the ISL12023 device using a surface mount crystal. Two main precautions should be followed: 1. Do not run the serial bus lines or any high speed logic lines in the vicinity of the crystal. These logic level lines can induce noise in the oscillator circuit to cause misclocking. 2. Add a ground trace around the crystal with one end terminated at the chip ground. This will provide termination for emitted noise in the vicinity of the RTC device..
FIGURE 19. SUGGESTED BATTERY-BACKUP CIRCUIT
The diode, DBAT will add a small drop to the battery voltage but will protect the circuit should battery voltage drop below 1.8V. The jumper is added as a safeguard should the battery ever need to be disconnect from the circuit. The VDD negative slew rate should be limited to below the data sheet spec (10V/ms) otherwise battery switchover can be delayed, resulting in SRAM contents corruption and oscillator operation interruption.
Oscillator Crystal Requirements
The ISL12023 uses a standard 32.768kHz crystal. Either through hole or surface mount crystals can be used. Table 26 lists some recommended surface mount crystals and the parameters of each. This list is not exhaustive and other surface mount devices can be used with the ISL12023 if their specifications are very similar to the devices listed. The crystal should have a required parallel load capacitance of 12.5pF and an equivalent series resistance of less than 50k. The crystal's temperature range specification should match the application. Many crystals are rated for -10C to +60C (especially through hole and tuning fork types), so an appropriate crystal should be selected if extended temperature range is required.
TABLE 26. SUGGESTED SURFACE MOUNT CRYSTALS MANUFACTURER Citizen Epson Raltron SaRonix Ecliptek ECS Fox PART NUMBER CM200S MC-405, MC-406 RSM-200S 32S12
FIGURE 20. SUGGESTED LAYOUT FOR ISL12023 AND CRYSTAL
In addition, it is a good idea to avoid a ground plane under the X1 and X2 pins and the crystal, as this will affect the load capacitance, and therefore, the oscillator accuracy of the circuit. If the FOUT pin is used as a clock, it should be routed away from the RTC device as well. The traces for the VBAT and VDD pins can be treated as a ground, and should be routed around the crystal.
Crystal Oscillator Frequency Compensation
CRYSTAL CHARACTERISTICS The ISL12023 device contains a complete system for adjusting the frequency of the crystal oscillator to compensate for temperature variation. A typical 32.768kHz crystal used with RTC devices has a temperature versus frequency curve, as shown in Figure 21.
0 -20 -40 -60 PPM -80 -100 -120 -140
ECPSM29T-32.768K ECX-306 FSM-327
Layout Considerations
The crystal input at X1 has a very high impedance, and oscillator circuits operating at low frequencies such as 32.768kHz, are known to pick up noise very easily if layout precautions are not followed. Most instances of erratic clocking or large accuracy errors can be traced to the susceptibility of the oscillator circuit to interference from adjacent high speed
-160 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 TEMPERATURE (C)
FIGURE 21. RTC CRYSTAL TEMPERATURE DRIFT
This curve equation follows Equation 6:
f = * ( T - T 0 )
2
(EQ. 6)
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ISL12023
Where is the temperature constant, with a typical value of 0.034 ppm/C. T0 is the turnover temperature of the crystal, which is the apex of the parabolic curve. If the two factors and T0 are known, it is possible to correct for crystal temperature error to very high accuracy. The crystal will have an initial accuracy error at room temperature, typically specified at 20C. The other important characteristic is the capacitances associated with the crystal. The load capacitance is normally specified at 12.5pF, although it can be lower in some cases. There is also a motional capacitance, which affects the ability of the load capacitance to pull the oscillation frequency, and it is usually in the range of 2.2fF to 4.0fF. RTC CLOCK CONTROL The ISL12023 uses two mechanisms to adjust the RTC clock and correct for the temperature error of the external crystal. The Analog Trimming (AT) adjusts the load capacitance seen by the crystal. Analog switches connect the appropriate capacitance to change the frequency in increments of 1ppm. The adjustment range for the ISL12023 is +32/-31ppm. The AT can be further refined using the BETA register. The BETA register function is to allow for changes in CM (motional capacitance), which will affect the incremental frequency change of the AT adjustment. A simple test procedure uses the BETA register to bring the step size back to 1ppm. Normally, the crystal frequency is adjusted at room temperature to zero out the frequency error using the IATRxx register bits (initial Analog Trimming). In addition, the IATRxx setting is varied up and down to record the variation in oscillator frequency compared to the step change in IATRxx. Once that value is known then the BETA register is used to adjust the step size to be as close to 1ppm per IATRxx step as possible. After that adjustment is made, then any ISL12023 temperature compensation adjustments will use a 1ppm change for each bit change in the internal AT adjustment. The Digital Trimming (DT) uses clock pulse add/subtract logic to change the RTC timing during temperature compensation. The DT steps are much coarser than the AT steps and are therefore used for large adjustments. The DT steps are 30.5ppm, and the range is from -305ppm to +305ppm. The Frequency Output function will show the clock variation with DT settings, except for the 32,768Hz setting, which only shows the AT control. ACTIVE TEMPERATURE COMPENSATION The ISL12023 contains an intelligent logic circuit which takes the temperature sensor digital value as the only input variable. It then uses the register values for the crystal variables and T0, and combines those with calibration from the BETA and ITR0 registers to produce "Final" values for the AT and DT, known as FATR (Final AT Register) and FDTR (Final DT Register). Those AT and DT values combine to directly compensate for the temperature error shown in Figure 21. The temperature sensor produces a new value every 60s (or up to 10 minutes in battery mode), which triggers the logic to calculate a new AT/DT value set. For every temperature calculation result, there can only be one corresponding AT/DT correction value.
Measuring Oscillator Accuracy
The best way to analyze the ISL12023 frequency accuracy is to set the IRQ/FOUT pin for a specific frequency, and look at the output of that pin on a high accuracy frequency counter (at least 7 digits accuracy). Note that the IRQ/FOUT is an drain output and will require a pull-up resistor. Using the 1.0Hz output frequency is the most convenient as the ppm error is as expressed in Equation 7:
ppm error = ( F OUT - 1 ) * 1e6 (EQ. 7)
Other frequencies may be used for measurement but the error calculation becomes more complex. When the proper layout guidelines are observed, the oscillator should start-up in most circuits in less than 1s. When testing RTC circuits, a common impulse is to apply a scope probe to the circuit at the X2 pin (oscillator output) and observe the waveform. DO NOT DO THIS! Although in some cases you may see a usable waveform, due to the parasitics (usually 10pF to ground) applied with the scope probe, there will be no useful information in that waveform other than the fact that the circuit is oscillating. The X2 output is sensitive to capacitive impedance so the voltage levels and the frequency will be affected by the parasitic elements in the scope probe. Use the FOUT output and a frequency counter for the most accurate results.
Temperature Compensation Operation
The ISL12023 temperature compensation feature needs to be enabled by the user. This must be done in a specific order, as follows: 1. Read register 0Dh, the BETA register. This register contains the 5-bit BETA trimmed value which is automatically loaded on initial power-up. Mask off the 5LSB's of the value just read. 2. Bit 7 of the BETA register is the master enable control for temperature sense operation. Set this to "1" to allow continuous temperature frequency correction. Frequency correction will then happen every 60s with VDD applied. 3. Bits 5 and 6 of the BETA register control temperature compensation in battery-backup mode (see Table 15). Set the values for the operation desired. 4. Write back to register 0Dh making sure not to change the 5 LSB values, and include the desired compensation control bits. Note that every time the BETA register is written with the TSE bit = 1, a temperature compensation cycle is instigated
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ISL12023
and a new correction value will be loaded into the FATR/FDTR registers (if the temperature changed since the last conversion). Also note that registers 0Bh and 0Ch, the ITR0 and ALPHA registers, should not be changed. If they must be written be sure to write the same values that are recalled from initial power-up. The ITR0 register may be written if the user wishes to re-calibrate the oscillator frequency at room temperature for aging or board mounting. The original recalled value can be re-written if desired after testing. For further information on the operation of the ISL12023 and temperature compensated RTC's, see Intersil Application Note AN1389, "Using Intersil's High Accuracy Real Time Clock Module". http://www.intersil.com/data/an/AN1389.pdf
TABLE 27. DST EXAMPLE VARIABLE VALUE REGISTER 15h 16h VALUE 84h 48h
Month Forward and DST April Enable Week and Day Forward 1st Week and and select Day/Week, not Sunday Date Date Forward Hour Forward Month Reverse not used 2am October
17h 18h 19h
00h 02h 10h 78h
Week and Day Reverse Last Week and 1Ah and select Day/Week, not Sunday Date Date Reverse Hour Reverse not used 2am 1Bh 1Ch
00h 02h
Daylight Savings Time (DST) Example
DST involves setting the forward and back times and allowing the RTC device to automatically advance the time or set the time back. This can be done for current year, and future years. Many regions have DST rules that use standard months, weeks and time of the day which permit a pre-programmed, permanent setting. Table 27 shows an example setup for the ISL12023. The Enable bit (DSTE) is in the Month forward register, so the BCD value for that register is altered with the additional bit. The Week and Day values along with Week/Day vs Date select bit is in the Week/Day register, so that value is also not straight BCD. Hour and Month are normal BCD, but the Hour doesn't use the MIL bit since Military time PM values are already discretely different from AM/PM time PM values. The DST reverse setting utilizes the option to select the last week of the month for October, which could have 4 or 5 weeks but needs to have the time change on the last Sunday. Note that the DSTADJ bit in the status register monitors
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FN6682.2 June 24, 2009
ISL12023 Thin Shrink Small Outline Plastic Packages (TSSOP)
N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c MIN 0.002 0.031 0.0075 0.0035 0.195 0.169 0.246 0.0177 14 0o 8o 0o MAX 0.047 0.006 0.041 0.0118 0.0079 0.199 0.177 0.256 0.0295 MILLIMETERS MIN 0.05 0.80 0.19 0.09 4.95 4.30 6.25 0.45 14 8o MAX 1.20 0.15 1.05 0.30 0.20 5.05 4.50 6.50 0.75 NOTES 9 3 4 6 7 Rev. 2 4/06
e
b 0.10(0.004) M C AM BS
A1 0.10(0.004)
A2 c
D E1 e E L N
0.026 BSC
0.65 BSC
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 28
FN6682.2 June 24, 2009

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